A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values
Wafer acceptance testing (WAT) is a process that is used to assess the quality and reliability of manufactured wafers. This technique for the early detection and screening of chips allows for improvements in their reliability and performance during the manufacture of semiconductor devices. The automatic test equipment (ATE) used for processing millions of wafers is susceptible to a number of issues, including the absence of data values, the presence of redundant parameters, and categorical imbalance. These issues increase the cost of data processing and impede an investigation into the relationship between WAT and feature diagnostics. In this study, we propose a method with a low test escape rate based on a multi-objective optimization algorithm to reduce the cost of testing and minimize the number of defective dice that go undetected. The proposed method retains outliers, dynamically selects the range of the neighborhood to reduce the cost of testing, and uses Shapley values to analyze a WAT dataset to determine the importance of features of the data. The multi-objective optimization algorithm ranks features by their importance and applies an adaptive method to eliminate features with a low overall correlation, thereby reducing the risk that defective dice are undetected.
Authors
- Mu Nie (ORCID: https://orcid.org/0000-0002-7822-4915)
- Cheng Zhuo (ORCID: https://orcid.org/0000-0002-2610-7522)
- Xiaoqing Wen (ORCID: https://orcid.org/0000-0001-8305-604X)
- Tianming Ni (ORCID: https://orcid.org/0000-0001-6272-8660)
- Yu Li (ORCID: https://orcid.org/0000-0001-9122-5923)
- Wangsheng Rui
Institutions
- Kyushu Institute of Technology (JP)
- Anhui Polytechnic University (CN)
- Zhejiang University (CN)
Publication Details
- Journal
- ACM Transactions on Design Automation of Electronic Systems
- Published
- 2025-02-12
- DOI
- https://doi.org/10.1145/3716826
- Citations
- 3
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 6.81