Lightweight NPU Method Based on Hyper-Threading Technology

With the rapid development of deep learning, the processing power of Neural Processing Unit(NPU) continues to improve. However, this leads to an increasing scale of logical resources for NPU, making it challenging to deploy NPU on Field-Programmable Gate Array(FPGA). To address this issue and enable the deployment of high-computational-power NPU on FPGA, this paper proposes a lightweight NPU method based on hyper-threading technology, considering the characteristics of NPU hardware architecture. This method effectively reduces the logical resources usage of the NPU while ensuring only a minimal decrease in computational power, thus enabling successful FPGA deployment. The overall experiment is based on the Virtex UltraScale+ HBM VCU128 FPGA platform. After testing, it was found that the NPU, previously undeployable, could be successfully deployed after lightweight processing. The resource usage ratio of LUTs decreased by about 10%, and the computational power only decreased by 4%. In other words, by using this method, the scale of logical resource usage of the NPU was effectively reduced while ensuring a minimal decrease in computational power, improving the deployment situation of the NPU on FPGA. This approach has certain reference value and significance for the lightweight design of NPU.

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Publication Details

Published
2024-11-22
DOI
https://doi.org/10.1109/icsidp62679.2024.10869015
Primary Topic
Network Packet Processing and Optimization
Type
article
Field-Weighted Citation Impact
0.00

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article

Lightweight NPU Method Based on Hyper-Threading Technology

Zhu Yang, Yizhuang Xie, Yongrui Li, Wenlong Li et al.
Network Packet Processing and Optimization
article

Lightweight NPU Method Based on Hyper-Threading Technology

Zhu Yang, Yizhuang Xie, Yongrui Li, Wenlong Li, Ao Zhang, Zhihan Zhang
article en

Abstract

With the rapid development of deep learning, the processing power of Neural Processing Unit(NPU) continues to improve. However, this leads to an increasing scale of logical resources for NPU, making it challenging to deploy NPU on Field-Programmable Gate Array(FPGA). To address this issue and enable the deployment of high-computational-power NPU on FPGA, this paper proposes a lightweight NPU method based on hyper-threading technology, considering the characteristics of NPU hardware architecture. This method effectively reduces the logical resources usage of the NPU while ensuring only a minimal decrease in computational power, thus enabling successful FPGA deployment. The overall experiment is based on the Virtex UltraScale+ HBM VCU128 FPGA platform. After testing, it was found that the NPU, previously undeployable, could be successfully deployed after lightweight processing. The resource usage ratio of LUTs decreased by about 10%, and the computational power only decreased by 4%. In other words, by using this method, the scale of logical resource usage of the NPU was effectively reduced while ensuring a minimal decrease in computational power, improving the deployment situation of the NPU on FPGA. This approach has certain reference value and significance for the lightweight design of NPU.

Beijing Institute of Technology (CN), Beijing Founder Electronics (China) (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 70%
Network Packet Processing and Optimization
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Lightweight NPU Method Based on Hyper-Threading Technology — Zhu Yang, Yizhuang Xie, et al. · (2024) | TGRS Research Map | TGRS