Low-Cost, High-Performance Algorithm and Hardware Architecture for SAO Mode Decision

Sample adaptive offset (SAO) is applied for reducing sample distortion and attenuating ringing artifacts in both HEVC and VVC standards. The rate-distortion optimization process is used to select the best SAO parameter. It accounts for the majority of SAO complexity and determines the SAO filtering performance. Therefore, the rate-distortion cost calculation should be well handled to achieve both low cost and high coding performance. In this paper, we propose a simplified and optimized rate estimation algorithm based on the characteristics of SAO parameter syntax and entropy coding process. And we propose a hierarchical flow for rate-distortion cost calculation to further reduce the computational cost and storage cost for SAO mode decision hardware. The results show that the proposed algorithm achieves an average YUV loss of -0.10%, and the proposed SAO mode decision hardware architecture can be implemented by only 21.8k gates using TSMC 65nm process under 400 MHz.