A 140-GHz CMOS Four-Way Power Combining Doherty Power Amplifier With Adaptive Biasing

This brief presents a D-band power amplifier (PA) with high output power and high back-off efficiency in 40nm GP CMOS technology. The PA is based on a four-way parallel power-combining Doherty architecture. Two sub-amplifiers with high output power have been realized using a highly balanced impedance-transforming power combiner based on the SLOT-GCPW structure. A transmission-line-like impedance inverter and a quadrature coupler with a slow wave coplanar waveguides (S-CPWs) are proposed to obtain compact size. Meanwhile, the adaptive bias technique is used to overcome the difficulties of implementing conventional Doherty architectures at terahertz (THz). The measured Doherty PA realizes a peak small-signal gain of 15.3 dB with 17 GHz 3-dB bandwidth. At 140 GHz, the PA achieves 16.1 dBm saturated output power (Psat) with peak power-added-efficiency (PAE) of 7% and 3% PAE at 6-dB power back-off (PBO) from Psat. To the authors’ best knowledge, this is the first D-band CMOS integrated PA with high PBO efficiency.