High Performance Array Multiplier Implemented Using Full Swing Adders for Fast Computations in Digital Signal Processing and Neural Networks

The Array Multiplier (AM) performs the role of a crucial cornerstone of digital signal processing as well as neural networks and more. A framework employing AM is elliptic curve cryptography, which depends on quick and secure multiplication processes that array multipliers can provide. This analysis demonstrates that temperature is a critical factor; consequently, the functionality of the AM also varies with temperature. In the MFA-based array multiplier, while the gate length is reduced from 90nm to 16nm at 27°C, the delay is decreased by 47.5%, the power consumption is reduced by 95.08%, and the PDP falls by 97.42%. Conversely, when the supply voltage drops from 1.2V to 0.7V, latency increases by 46.43%, the power consumption diminishes by 94.17%, and the PDP reduces by 10.89% respectively. In an AM implemented using HFA, as the gate length decreases from 90nm to 16nm at 27oC, the delay decreases by 35.83%, power consumption lowers by 95.21%, and the PDP decreases by 96.98%. When the supply voltage is swept from 1.2V to 0.7V, the delay increases by 61.63%, the power consumption decreases by 94.57%, and the PDP decreases by 85.85% respectively. The majority of modern computing systems require multipliers, which are known to be significant contributors to power consumption.