Performance Analysis of Exact/Approximate Multipliers for Image Processing Applications

Approximate multipliers play a key role in reducing hardware complexity with minimum circuit components. By compensating the computational accuracy, approximate multipliers help in reducing the power consumption, processing time, and area. This will be helpful in image processing applications where accuracy is compromised. This work analyzes the design of exact and approximate multipliers in terms of performance metrics, such as area, power, and delay. Moreover, Type 1, Type 2, and Type 3 approximate Vedic and array multipliers are designed, and their performance metrics are analyzed with the help of cadence tool (Cadence Encounter<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> RTL Compiler v12.10-s012_1) for 45 nm technology. Simulation results signify that the proposed Type-3 approximate array multiplier decreases the area by 64.38%, power by 80.03%, delay by 83.5% and Power Delay Product (PDP) by 96.79%. To practically evaluate the approximate designs, image addition and image multiplication are performed using Python code in Google Col-laboratory and a comparative study its performance parameters like Peak Signal-to-Noise Ratio (PSNR), Mean Squared Error (MSE), Mean Absolute Error (MAE), and Structural Similarity Index Measure (SSIM) is analyzed.