Performance Evaluation of a Low-Power 10T SRAM Cell using CNTFET Technology

This work presents a performance-optimized 10T SRAM cell based on CNTFET technology, simulated on HSPICE. The presented design significantly improved the average power consumption, delay, power-delay product, and voltage source power dissipation compared to conventional MOS-based SRAM cells. The CNTFET 10T SRAM cell achieves an average reduction in power by 95.38%, an improvement in delay by 97.74%, with a remarkable PDP improvement of 99.99% compared to the 10T SRAM MOS. Also, the power dissipation by the voltage source is reduced by 99.51%, hence making the CNTFET-based design a highly energy-efficient alternative. These results thus prove the viability of CNTFET in low-power and high-performance SRAM designs.