Performance of FPGA-based Implementations of Data Classification Techniques using HDL Coder

The aim of this tutorial paper is to check the efficiency of data classification techniques implemented on a field programmable gate array (FPGA) using a high-level synthesis (HLS) tool. We implement data classification techniques using Simulink with HDL Coder onto a Basys 3 FPGA board. Using a scalable and modular approach, three different algorithms are implemented in this paper with varying parameters, and their resource utilization is recorded. The three algorithms are the fast Fourier transform (FFT), the discrete cosine transform (DCT), and the K-Nearest Neighbor (KNN) algorithm.