A Neuron CMOS Type Full Subtractor with Floating Gate Calibration Circuit

As a result of technological advancements, the amount of computation has increased, which has led to a higher load on the Arithmetic Logical Units (ALUs) in integrated circuits. To reduce this load, our research focuses arithmetic circuits based on neuron CMOS inverter (νCMOS), which is multi-valued logic device that can be fabricated in a conventional CMOS process. In this paper, we propose a neuron CMOS type full subtractor with an additional floating gate (FG) stabilization circuit, called the FGC circuit. This full subtractor is an improvement on our previously proposed neuron CMOS type full adder with FGC circuit, but the method of applying the widely known concept of two’s complement was difficult to realize due to the circuit characteristics of νCMOS. Therefore, by deriving and constructing the νCMOS circuit from the truth table of the full subtractor, the subtraction function can be realized. In the proposed full subtractor, the circuit configuration and operation are described and verified by HSPICE simulation. Additionally, we elucidate the multistage method of the proposed circuit, construct a 4-bit full subtractor, and verify its operation.