Low-Power Optimized UART Implementation on FPGA Device

In the era of technological advancement, the demand for IoT (Internet of Things) and power-efficient devices is increasing rapidly. The data transfer in IoT devices can be done using serial communication methods, for this UART (Universal asynchronous receiver-transmitter) devices play a vital role. In this work, we are implementing a UART design on Artix-7 FPGA which is beneficial for IoT devices and can be a handful for promoting the ideas of Green Communication (GC). To optimize the power of UART for better IoT services we have used MOBILE DDR IO standard at different ranges of frequency between 100 MHz to 10 GHz. From the power analysis, it is observed that the UART delivers low power when it is operated at low-frequency values and consumes more power at high-frequency values.