Advanced FFT Processor Design for Enhanced Efficiency in Next-Generation Networks

Advancements in network technology, such as 5G and 6G systems, have increased the need for large-scale data communication. This has led to a higher demand for efficient FFT processors capable of handling big data. In this paper, we propose a low-power variable-length FFT architecture with distributed memory to enhance data processing efficiency. The architecture employs an auto-correction rotator to efficiently and accurately generate the corresponding twiddle factors without excessive memory storage. To further reduce power consumption, distributed memory is used for storing computational data, with dynamic pointers facilitating data access. Simulations demonstrate improvements in processing speed and memory efficiency, addressing the demands for efficient data transmission. The proposed FFT chip design shows promise for application in next-generation network systems.