An Approximate Method for The Fault Tolerance of SRAM-Based Near-Memory Multiply-Accumulate Units

To address the von Neumann bottleneck, computing-in-memory is emerging as a prominent trend. While numerous studies have explored SRAM-based near-memory multiply-accumulate unit (MAC) design in recent years, they often overlook fault-tolerance techniques. In this paper, we propose integrating an approximate method into near-memory MAC circuits to prevent chips from becoming unusable due to a few faulty memory cells. If a memory cell responsible for calculating the most-significant-bit (MSB) fails, we reallocate the memory cell originally designated for calculating the least-significant-bit (LSB) to compute the MSB instead, thus minimizing computation errors. Experimental results demonstrate that the proposed approximate fault-tolerance mechanism incurs only a small additional area overhead but significantly reduces errors caused by memory cell faults.