Designing and Analysis of Leakage Compensated FC OP-AMP BASED Voltage Reference Designs

This paper presents the design of an FC op-amp-based voltage reference circuit, incorporating an inherent leakage compensation technique using diode-connected MOSFETs. This method compensates for high-temperature leakage currents and reduces power consumption while eliminating current mirror-induced mismatch. As a result, key parameters like temperature range, supply dependency, and PSRR are improved. A comparative analysis between designs with and without leakage compensation shows a temperature coefficient of 18.7 ppm/'C and an extended operating range from −50°C to 175°C. PSRR values of −80dB at 10Hz, −76.8dB at 1 KHz and −51.17dB at 1MHz was achieved. The line sensitivity is 0.036%V, with a 16.9mV variation across the temperature range. Power consumption is significantly reduced. Cadence Virtuoso with standard 180nm CMOS technology is used to conduct Simulations.

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Publication Details

Published
2024-11-21
DOI
https://doi.org/10.1109/delcon64804.2024.10866654
Primary Topic
Low-power high-performance VLSI design
Type
article
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article

Designing and Analysis of Leakage Compensated FC OP-AMP BASED Voltage Reference Designs

Rupali Singh, Anushree Anushree, Jasdeep Kaur
Low-power high-performance VLSI design
article

Designing and Analysis of Leakage Compensated FC OP-AMP BASED Voltage Reference Designs

Rupali Singh, Anushree Anushree, Jasdeep Kaur
article en

Abstract

This paper presents the design of an FC op-amp-based voltage reference circuit, incorporating an inherent leakage compensation technique using diode-connected MOSFETs. This method compensates for high-temperature leakage currents and reduces power consumption while eliminating current mirror-induced mismatch. As a result, key parameters like temperature range, supply dependency, and PSRR are improved. A comparative analysis between designs with and without leakage compensation shows a temperature coefficient of 18.7 ppm/'C and an extended operating range from −50°C to 175°C. PSRR values of −80dB at 10Hz, −76.8dB at 1 KHz and −51.17dB at 1MHz was achieved. The line sensitivity is 0.036%V, with a 16.9mV variation across the temperature range. Power consumption is significantly reduced. Cadence Virtuoso with standard 180nm CMOS technology is used to conduct Simulations.

Indira Gandhi Delhi Technical University for Women (IN)
Affordable and clean energy
Openalex Percentile: Top 75%
Low-power high-performance VLSI design
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