A High Performance Hardware Implementation of SHA-256 Algorithm

SHA-256 is a well-reported algorithm extensively utilized in security applications. This paper presents a high performance hardware implementation of SHA-256 algorithm. The SHA-256 algorithm is reconstructed based on 64-level high-speed full pipeline computing architecture design to improve the algorithm throughput. In addition, the timing path of the compression function of SHA-256 is optimized to break the critical path, which increase the operating frequency of SHA-256 and further improve the throughput. Finally, Carry-Save Adder (CSA) technology is employed in the message expansion to further improve the timing and related parameters. The proposed architecture of SHA-256 is implemented on Xilinx Virtex-7 FPGA device, and the experimental results indicate that the designed SHA-256 demonstrates a frequency of 429 MHz, a throughput of 219.65 Gbps, and an efficiency of 24.84 Mbps/slice.