FPGA-Based RISC Processor with Pseudo Open Drain for Power Optimization

In the age of Internet of Things (IoT), IoT gadgets are getting popularity. The IoT devices better work when they have better lifetime and this better lifetime of such devices are achieved when they consume low amount of power. The low power consumption (PC) can be achieved when the processor of such IoT devices also consumes low power. This work highlights all such points which enhances the life of IoT devices. In this work we are designing and implementing a Reduced Instruction Set Computing (RISC) processor on Kintex Ultrascale+ FPGA devices. To optimize the power of RISC processor for better IoT services we have used Pseudo Open Drain (POD) IO standard at different range of frequency between 100 MHz to 5 GHz. After the power calculation, it is detected that the RISC processor delivers low power when it is operated at low frequency values and consumes more power at high frequency values.