Synchronous Up/Down Counter Using Clocked CMOS Toggle Flip-Flop With 3T-SAPON Technique For Low Power Consumption

In this paper, 16 bit counter that operates with low power consumption in a synchronous manner is designed. Counter is designed with different segments namely local clock generator(LCS), local clock pre-evaluators(LCPE), local clock selector(LCS) and a toggle flip flop. In Clocked Complementary Metal Oxide Semi-Conductor Toggle Flip Flop (CMOS T-FF), it is inculcated with three Transistor Stackly Arranged Low Power ON Transistor (3T-SAPON) technique for efficient power consumption. This technique will reduce the unnecessary power consumption within the Clocked CMOS T-FF. The counter supports both up and down counting. Power consumption is reduced by 57%. The designing is done in cadence virtuoso environment in 180nm technology. Cadence Virtuoso is a comprehensive suite of tools used for circuit design, especially in the semiconductor industry for creating complex electronic circuits.