Asynchronous SAR ADC with Parallel Comparators Inspired by Hopfield Network

This paper studies the Analog-to-Digital Converter (ADC) based on the asymmetric Hopfield network, using a combination of concise analog elements. A significant technical challenge arises from the large circuit size and the necessity for multiple reference voltages in its previous designs. The study investigates a method for implementing a Hopfield network ADC using a charge redistribution architecture with only a positive reference voltage (no negative reference voltage) to compete against state-of-the-art SAR ADCs. The proposed ADC is an asynchronous capacitor-type SAR ADC with multiple comparators in parallel, each equipped with higher-bit look-ahead capability, resulting in faster ADC conversion speed. The feasibility of the investigated ADC circuit, which has an 8-bit resolution, was evaluated in terms of conversion speed, power consumption, and effective number of bits through SPICE simulation using SOTB 65nm CMOS technology.