CPLD Implementation of Data Demultiplexing
Modern communication technology focuses on the development of digitalization, and digital multiplexing and demultiplexing technology is an important technology in communication technology. By combining multiple low-speed signals into one high-speed signal, it can improve bandwidth utilization and data transmission efficiency. The paper presents an eight channel tap of a complete 512KHz frame data. By setting up a frame synchronization module, a data counting module, a serial to parallel caching module, a parallel to serial caching module, and an output module, the eight low-speed signals are merged into one high-speed signal. Finally, the code is written using Quartus_II software, and the results are verified through Modelsim simulation and hardware download verification.
Authors
- Wei Pan (ORCID: https://orcid.org/0000-0001-9798-770X)
- Ming Cui (ORCID: https://orcid.org/0000-0002-3669-3473)
- Wei Luo (ORCID: https://orcid.org/0000-0003-4016-765X)
- Yan Zhong
Institutions
- Jiangsu Agri-animal Husbandry Vocational College (CN)
- Nanjing University of Aeronautics and Astronautics (CN)
Publication Details
- Published
- 2024-12-06
- DOI
- https://doi.org/10.1109/iciba62489.2024.10868023
- Primary Topic
- Distributed and Parallel Computing Systems
- Type
- article
- Field-Weighted Citation Impact
- 0.00