Porting Lattice QCD benchmark to upcoming STX stencil/tensor accelerator

Developed under the European Processor Initiative (EPI), the STX stencil/tensor accelerator aims to achieve a 5-10x higher energy efficiency over general purpose compute units. The architecture consists of specialized MIMD compute units which are supported and controlled by RISC-V cores. We describe a co-design effort between hardware, software, and application development focused around porting a LQCD benchmark to this new architecture.