Software-Hardware Complex for Accelerating System-on-Chip Design Verification

Speeding up the process of verification of digital devices is a relevant task, which is being tackled by leading CAD developers creating specialized software-hardware complexes (emulators) that can reproduce the functionality of RTL hardware descriptions at simulation speeds in the megahertz range. This speed provides test execution times that are several orders of magnitude faster than with logical simulation. However, due to the high cost of emulators, they can only be used by large companies. In this study, a structure and a prototype of a software-hardware complex are proposed for accelerating the functional verification of complex functional IP blocks and systems-on-chip based on the available design tools, which will reduce the cost of solutions to speed up verification and simplify their use. Acceleration is achieved by transferring the calculations of the results of the actions of the device being tested from the simulator to the emulated device in the FPGA and by interaction between the simulator and the device being tested through a software interface. A prototype is implemented, based on the proposed structure, and its performance evaluation demonstrates that the simulation time is reduced by a factor of eight. The obtained result indicates the promising prospects of further research in this direction.