Hardware Complexity Reduction of Polar Encoder Architecture for 5G Technology

For a variety of underlying channels, Arikan's polar codes preserve “low encoding and decoding complexity” while reaching the capacity of symmetric channels. Polar code's channel reaching capacity has made it the best error-correcting code in information theory in recent years. As code length rises, the entirely parallel polar codebased encoder architecture experiences substantial hardware complexity, while processing bits in parallel. While partial parallel polar code-based architecture is limited by memory units in high-throughput applications, fully parallel polar code-based design leads to problems with logic complexity. This study uses the Xilinx evaluation board as the polar encoding technique and proposes and implements an efficient polar code-based encoder architecture on an FPGA. Our findings demonstrate the effectiveness of the solution in terms of the evaluation board's latency and resource usage. We analyze the polar code-based encoder designs' encoding procedure and propose a novel design that can encode longer polar codes with less complicated hardware.