Improving the Performance of Network-on-Chip by Utilizing Fault Zone Tiling to Reuse Trace Buffers

Network-on-Chip (NoC) is employed in multi-core systems to enhance the data transfer capacity and adaptability. The Network-on-Chips (NoCs) experience dependability issues due to software faults. Tiling is a procedure used to enhance the accuracy of data in NoCs (Networks-on-Chip). The fault-masking technique prevents the need for rechecking by the block. At this location, the presence of X tracer and the process of tiling are ongoing. The proposed work is implemented by simulation using Xilinx 12.1.