Design and Implementation of Sped Technique using Hybrid Adder for Area Reduction

Data processing processors use the Tree adder as a basic building block for fast arithmetic operations. As the scale of integration develops, more and more signal processing systems are being built on VLSI chips, which necessitates a high computational capability and large energy consumption. In addition to the two main design criteria of performance and area, power consumption must now be taken into account when designing today's VLSI systems. In order to reduce the data processing unit's power consumption, the transistor count of the adder must be reduced. Thus, the Tree adder framework's power and latency might be decreased. In the proposed design, an LFA (Ladner Fischer) adder is used instead of a single one.