Suppression of Drain-Bias-Induced <i>V</i>TH Instability in Schottky-Type <i>p</i>-GaN Gate HEMTs With Voltage Seatbelt

A cost-effective yet efficient approach is proposed for suppressing the drain-bias-induced threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula>) instability in Schottky-type p-gallium nitride (GaN) gate high electron mobility transistors (HEMTs). The proposed device consists of a source-connected metal layer on a dielectric layer in the gate-to-drain access region, which operates as a voltage seatbelt that restricts the voltage coupling to the p-GaN region from the drain within a defined range. By adjusting the dielectric thickness in the proposed structure, the voltage potential experienced by the p-GaN region is confined within a range of 3.1–22.3 V at a drain voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {DS}}$ </tex-math></inline-formula>) of 400 V. In the scenario with a 3.1-V clamping voltage, the proposed configuration demonstrates a remarkable reduction of over 95% in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula> shift caused by the floating nature of p-GaN, along with a reduction of 88% in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula> shift induced by trapping effects. The proposed structure also enhances short-circuit robustness by reducing the saturation current density, while exerting only a minimal effect on the devices’ on-resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {ON}}$ </tex-math></inline-formula>). The proposed structure offers room for balancing the tradeoff between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {ON}}$ </tex-math></inline-formula> and the short-circuit robustness in practical applications.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2025-02-10
DOI
https://doi.org/10.1109/ted.2025.3534168
Citations
5
Primary Topic
GaN-based semiconductor devices and materials
Type
article
Field-Weighted Citation Impact
6.29

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article

Suppression of Drain-Bias-Induced VTH Instability in Schottky-Type p-GaN Gate HEMTs With Voltage Seatbelt

Jinjin Tang, Mengyuan Hua, Guosong Zeng, Junting Chen et al.
5 citations
IEEE Transactions on Electron Devices
GaN-based semiconductor devices and materials
6.29
article

Suppression of Drain-Bias-Induced VTH Instability in Schottky-Type p-GaN Gate HEMTs With Voltage Seatbelt

Jinjin Tang, Mengyuan Hua, Guosong Zeng, Junting Chen, Yan Cheng, Kevin J. Chen, Junqiang Li, Jiongchong Fang, Haohao Chen, Zheng Wu
article en
5 citations

Abstract

A cost-effective yet efficient approach is proposed for suppressing the drain-bias-induced threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula>) instability in Schottky-type p-gallium nitride (GaN) gate high electron mobility transistors (HEMTs). The proposed device consists of a source-connected metal layer on a dielectric layer in the gate-to-drain access region, which operates as a voltage seatbelt that restricts the voltage coupling to the p-GaN region from the drain within a defined range. By adjusting the dielectric thickness in the proposed structure, the voltage potential experienced by the p-GaN region is confined within a range of 3.1–22.3 V at a drain voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {DS}}$ </tex-math></inline-formula>) of 400 V. In the scenario with a 3.1-V clamping voltage, the proposed configuration demonstrates a remarkable reduction of over 95% in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula> shift caused by the floating nature of p-GaN, along with a reduction of 88% in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula> shift induced by trapping effects. The proposed structure also enhances short-circuit robustness by reducing the saturation current density, while exerting only a minimal effect on the devices’ on-resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {ON}}$ </tex-math></inline-formula>). The proposed structure offers room for balancing the tradeoff between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {ON}}$ </tex-math></inline-formula> and the short-circuit robustness in practical applications.

IEEE Transactions on Electron DevicesVol. 72(3)
Hong Kong University of Science and Technology (HK), Southern University of Science and Technology (CN)
National Natural Science Foundation of China, Shenzhen Fundamental Research Program, Basic and Applied Basic Research Foundation of Guangdong Province
Affordable and clean energy
Openalex Percentile: Top 4%
GaN-based semiconductor devices and materials
6.29
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