An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier

A bitline sense amplifier (BLSA) with offset compensated charge transfer pre-sensing (OC-CTPS) scheme is implemented using 14-nm dynamic random access memory (DRAM) process. The offset compensation (OC) is operated by diode connection without additional size overhead for BLSA. The average fail bit count (FBC) attributed to a mismatch of charge transfer (CT) transistor was reduced by 94% after performing OC. Furthermore, the proposed OC-CTPS BLSA accomplished 250 and 500 ps of CT time (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\mathrm {CT}}$ </tex-math></inline-formula>) window, representing the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\mathrm {CT}}$ </tex-math></inline-formula> region where the FBC is lower than the standard FBC, at the temperatures of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 25~^{\circ }$ </tex-math></inline-formula>C and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100~^{\circ }$ </tex-math></inline-formula>C, respectively, without modifying any operations for CT. Moreover, our approach ensures robust and stable sensing even at operating voltages as low as 0.75 V, compared to conventional latch-based OC BLSA.