Stress-Related Local Layout Effects in FinFET Technology and Device Design Sensitivity

Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modulated by device design and local/ global environment. In this paper we investigate the impact of stress, developed during FinFET device fabrication, on electrical characteristics of transistors manufactured in 7nm silicon FinFET technology. Two sources of stress modulation are studied: (i) active region isolation (Diffusion Break) (ii) Metal Gate extension outside of the fins of the transistor. A 3D TCAD process model of a FinFET device was created and calibrated using electrical characteristics measured on foundry fabricated silicon wafers. The model was then applied to simulate mechanical stress in transistors with various design attributes for Diffusion Breaks (Single vs. Double Diffusion Break) and Gate Cuts, following by modeling of electrical characteristics. Very good agreement between simulations and measured silicon data has been obtained for PMOS and NMOS FinFET transistors. This work demonstrates that the layout sensitivity in discussed design cases can be explained by modulation of the mechanical stress and that the model can be used to predict successfully the stress distributions and their impact on electrical characteristics of FinFET devices. It can be applied to assist designers and technologists with Design-Technology Co-optimization, design rule and PDK development, and process optimization for best performance and reduced variability.