SEU Vulnerability of SRAM Designs at a 3-nm Bulk FinFET Node

Single-event upset (SEU) vulnerabilities are investigated for single-port (SP), two-port (TP), and content-addressable static random access memory (SRAM) arrays in a 3-nm bulk fin field-effect transistor (FinFET) technology for alpha particles and heavy-ion exposures. TP and content-addressable memory (CAM) cells have asymmetric designs, resulting in preferred states with reduced SEU vulnerability. Preferred states also significantly impact cluster sizes for multicell upsets (MCUs). These results show that small differences in cell designs lead to significant changes in SEU vulnerability.