Transferring Fine-Pitch Cu Nanoparticle Bumps for Low-Temperature Cu-Cu Bonding in Chip-Scale Integration

Cu-Cu bonding using nanomaterials as an intermediate has attracted increasing attention for its eased requirements for bonding temperature and surface roughness. In this work, we developed a novel low-temperature Cu-Cu bonding technique using transferable Cu nanoparticle bumps. These nanoparticle bumps were first fabricated on donor substrate through pulsed laser deposition (PLD) and then transferred to the target chip by low-temperature pre-sintering (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$160~^{\circ }$ </tex-math></inline-formula>C). The conventional dry transfer method using Si donor substrate was proved less feasible since the Cu-O–Si bond formed between Cu nanoparticles and SiO2 natural oxide layer on Si surface could cause transfer failure. An alternative wet transfer approach using Al as a sacrificial layer was proposed, wherein Al was dissolved by KOH solution and nanoparticle bumps were subsequently transferred. The self-release characteristic of wet transfer ensured a higher transfer yield. Transferred nanoparticle bumps on target chip maintained sintering activity and could realize reliable die shear strength (37.4 MPa) with target substrate at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$200~^{\circ }$ </tex-math></inline-formula>C, 15 MPa, and 5 min. The electrical resistance of sintered Cu joints showed negligible change before and after transfer. Joint strength decreased to 27.3 MPa due to oxidation after a thermal shock test (TST) (−65 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$150~^{\circ }$ </tex-math></inline-formula>C) for 500 cycles. The transfer strategy could enable a more flexible application of nanomaterials for all-Cu interconnection in chip-scale integration.