An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System

In this brief, an all-digital spread-spectrum clock generator (AD-SSCG) is presented for low-power wide-area network (LPWAN) chirp spread spectrum application. Facing the periodic frequency hopping in chirp modulation, a gain calibration is employed in feedforward path to avoid two-point modulation (TPM) loop-gain mismatches and phase error, ensuring a precise frequency tracking. Employed with the combination of a constant slope digital-to-time converter (CS-DTC) and an multi-bit mid-rise TDC, the embedded digital loop can provide a linear sawtooth chirp modulation while keeping a good phase noise (PN) performance. Fabricated in a 40nm CMOS process, the AD-SSCG achieves a random jitter of 508fs<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula>, with measured PN of −111.6dBc/Hz@1MHz. The EMI reduction achieves 39.1dB (4MHz + 2000ppm depth). The prototype chip consumes 2.45mW under 1.1V supply voltage.