An All-Digital and Wide-Range De-Skew Circuit With Dual-Edge Correction Scheme for Source Synchronous Interfaces

This brief presents an all-digital and wide-range de-skew circuit with dual-edge correction scheme for source synchronous interfaces to achieve precise synchronization between data and clock. The proposed scheme not only aligns the rising edges of data and clock signals, but also compensates for the falling edge position offsets of multi-bit parallel data, which can address the narrowing of data valid window caused by skew and pulse-width distortion. A two-stage digitally-controlled delay line is utilized to achieve wide-range de-skew. Besides, a half-cycle delay line method is adopted for clock duty-cycle correction, while generating a 90-degree phase shift to optimize the sampling margin. The test chip is fabricated in 180nm CMOS process, and each data path with the proposed de-skew circuit occupies 0.0453mm2. The chip testing results show that the timing skew between data and clock is reduced to within 28ps, and the pulse-width correction error is less than 1.7% when the duty cycle of the input clock pattern data signal ranges from 28% to 65%.