Energy-Efficient and Fault-Tolerant Sparse Coding for Spiking Neural Networks Accelerator

Spiking Neural Networks (SNNs) exhibit superior energy efficiency and fault tolerance compared to Artificial Neural Networks (ANNs). Due to their spike-based nature, input signals must be encoded into spike trains. However, traditional spiking coding schemes often encounter a trade-off between energy efficiency and fault tolerance. To overcome this limitation, we propose a novel coding scheme, Spiking Sparse Coding (SSC), which achieves both high sparsity and enhanced fault tolerance. SSC not only improves network performance but also reduces the number of spikes by 93.69%, resulting in a 76.47% increase in energy efficiency. Additionally, SSC enhances network fault tolerance, with accuracy improvements of up to 12.06% under identical noise interference conditions. We deployed the network on the ZCU102 FPGA platform, operating at a frequency of 200 MHz with a power consumption of 409 mW. On the MNIST dataset, we achieved a classification accuracy of 95.84%. The training speed and energy consumption were 12656 frames per second and 0.032 mJ per image, the inference speed and energy consumption were 19279 frames per second and 0.021 mJ per image.