A 0.6-8.1 GHz, 2 dB NF inductorless LNTA in 22 nm CMOS with novel bandwidth extension technique

This paper introduces a broadband low-noise transconductance amplifier (LNTA) d esigned f or s urface a coustic wave (SAW) filter-less wideband receivers (RXs). The design is based on common-source stage with resistive feedback (CS-RF) structure, utilizing the combination of a cascode stage and an auxiliary common-source stage to expand the bandwidth and achieve noise cancellation. The circuit implements derivative superposition by summing currents from transistors with different threshold voltages, thereby enhancing the input third-order intercept point (IIP3) of the LNTA. The overall circuit utilizes a complementary NMOS/PMOS architecture for current reuse, resulting in power savings. The chip is implemented in 22-nm CMOS technology. Post-simulation results indicate that the proposed LNTA achieves a transconductance gain (Gm) of 280 mS and a minimum noise figure (NF) of 2 d B w ithin a b andwidth upto8 G Hz. The maximum IIP3 across various frequency bands reaches $\mathbf{- 1 0. 8} \mathbf{~ d B m}$. Under a 0.9 V power supply, the power consumption is 4.6 mW. The circuit occupies an area of only $120 \mu \mathrm{~m} \times 90 \mu \mathrm{~m}$.