A Lightweight 3D D2D Interface for Active Interposer Chiplet Systems

This paper proposes a standardised, power-efficient and low-latency die-to-die (D2D) physical layer interface for active interposer and chiplet vertical interconnect. It realises the interoperation between chiplet and interposer in 28 nm and 40 nm respectively. To control the overhead, it adopts self-timed and parallel interface architecture with limited data rate and uses a lightweight deskew scheme. Post-layout simulation shows that this 3D D2D interface achieves a high data rate of 4Gbps per lane, a high energy efficiency of $0.74 \mathrm{pJ} / \mathrm{bit}$ and $0.81 \mathrm{pJ} / \mathrm{bit}$ in two directions respectively and a short latency of 3.2 ns.