Instruction-Aware Cooperative TLB and Cache Replacement Policies
Modern server and data center applications are characterized not only by big datasets, but also by large instruction footprints that incur frequent cache and Translation Lookaside Buffer (TLB) misses due to instruction accesses. Instruction TLB misses are particularly problematic since they cause pipeline stalls that significantly harm performance.
Authors
- Dimitrios Chasapis (ORCID: https://orcid.org/0000-0002-7191-0867)
- Marc Casas (ORCID: https://orcid.org/0000-0003-4564-2093)
- Georgios Vavouliotis (ORCID: https://orcid.org/0000-0002-5416-6634)
- Daniel A. Jiménez (ORCID: https://orcid.org/0000-0001-5658-4883)
Institutions
- Barcelona Supercomputing Center (ES)
- The Geneva Association (CH)
- Texas A&M University (US)
- Universitat Politècnica de Catalunya (ES)
Publication Details
- Published
- 2025-02-06
- DOI
- https://doi.org/10.1145/3669940.3707247
- Citations
- 2
- Primary Topic
- Caching and Content Delivery
- Type
- article
- Field-Weighted Citation Impact
- 2.97