A 7–20 GHz Ultra-High-Linearity Passive Mixer in 45 nm CMOS SOI

This article presents a wideband 7–20 GHz passive mixer with extremely high linearity performance. Series-stacking and floating gate techniques are adopted to increase the mixer switch linearity in the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> states. Furthermore, impedance step-down matching networks (MNs) are used to reduce the voltage swing around the switch, which enhances the mixer linearity and reduces the required number of series-stacked devices within the switch. Power-efficient stacked drivers with inter-stack LO coupling are used to drive the switching units. This modified design allows the driver to generate rail-to-rail swing at higher frequencies while maintaining high efficiency and low power consumption at low frequencies. The mixer prototype is fabricated in GlobalFoundries 45 nm CMOS SOI process and occupies an active area of 0.38 mm2. The mixer has a measured conversion loss of 8–11.7 dB at 7–20 GHz in down-conversion and up-conversion modes with an IP1dB of 19.7–25.1 dBm. The measured third-order input intercept point (IIP3) is 25.3–37 and 26.3–35.7 dBm at 7–20 GHz in down-conversion and up-conversion modes, respectively. The mixer operates at an LO input signal power of −1 dBm and consumes 25–74.4 mW from a 1.2-V supply (pre-drivers) and 46–355 mW from a 5-V supply (stacked drivers) at an LO frequency of 2–20 GHz. This translates to an IIP3 efficiency of 5–19 dB at 7–13-GHz RF. The mixer has a measured 2nd-order input intercept point (IIP2) of more than 43 dBm at 7–20 GHz. Application areas for this mixer include wideband receive beamforming chips for base station systems.