Design and Implementation of a Digital Phase-Locked Loop (DPLL) with Vernier Time-to-Digital Converter (TDC) for Dynamic Frequency Selection

In this paper, we propose a novel design of a Digital Phase-Locked Loop (DPLL) that integrates a Vernier Time-to-Digital Converter (TDC), priority encoder, and multiplexer (MUX) for precise dynamic frequency selection. The design leverages an 8-bit Vernier TDC to measure time differences, which are reduced to a 3-bit code using a priority encoder. The 3-bit code is then used as select lines for an 8:1 MUX, which dynamically chooses one of eight frequencies generated by an 8-bit ring oscillator. The output is used for clock generation in high-performance digital communication systems, offering improved accuracy and low power consumption.