Implementation and Performance Analysis of 8-bit Digital Parallel Array Multipliers

This paper presents the implementation and performance analysis of five digital parallel array multipliers: Conventional Array Multiplier, Modified Braun’s Multiplier, Vedic Multiplier, Booth’s Multiplier, and Baugh-Wooley Multiplier. It details the design principles, algorithms, and hardware implementations of each multiplier. The multipliers are evaluated based on speed, area, and power consumption via simulation using Xilinx Vivado software with Artix-7 FPGA Board. The results highlight the trade-offs in each design and provide insights into their suitability for various digital signal processing applications.