Instruction Decoding for Dual-Core Soft-Processors using Reed-Solomon codes

An area- and power-efficient unified fault-tolerant instruction decoder architecture for dual-core RISC-V RV32IM processors is proposed in this paper, targeting the improvement in reliability for Single Event Upset-susceptible environments. The proposed design uses a DMR system supported by Reed-Solomon error correction codes to enable real-time detection and correction of single-bit and multiple-bit errors. It underscores, in particular, the Reed-Solomon technique, which, for its strong capability of dealing with burst errors, gives a large advantage over parity-based error detection. Under computation by this decoder are the syndrome for the arriving instructions and then the use of the Berlekamp-Massey and Forney algorithms to compute locations and magnitude of the errors, which easily enable the exact correction of corrupted instructions. While TMR increases complexity and power consumption, DMR combined with Reed-Solomon provides similar fault tolerance levels with much reduced resource overhead. The architecture has been designed in Verilog HDL to ensure efficient resource utilization while maintaining superior fault coverage. Consequently, the results of the simulations ensure that the decoder is able to detect and correct the injected errors in the two instruction streams and guarantee fault tolerance operation with a power consumption of 28% less compared to classical majority voting-based TMR approaches. Therefore, this proposed architecture is highly suitable for aerospace and other embedded systems applications in which both power efficiency and fault tolerance are highly desired.