A Study on Functional Coverage-Driven Random Stimulus Generation Methods for Integrated Circuit Functional Verification

The rapid advancement of integrated circuit technology has led to an exponential increase in the scale and complexity of System-on-Chip designs, making chip verification the most time-consuming and resource-intensive phase in the development process. Traditional verification methods struggle to comprehensively cover all functional scenarios, adversely affecting verification efficiency and time-to-market. To address this issue, this paper proposes a novel rule-based functional coverage-driven random stimulus generation method. By establishing a correspondence between coverage points and constraint conditions, the proposed method dynamically updates the constraints for stimulus generation based on functional coverage information. This approach reduces redundant stimuli generation and accelerates verification convergence. Experimental results demonstrate that the method enhances verification efficiency, reduces redundant test stimuli, and more effectively covers unverified functional points. This research offers new insights for improving verification automation and the reusability of verification platforms, holding substantial practical engineering value.