A RISC-V Processor with Custom Instructions for Spiking Neural Network Acceleration

Spiking neural networks (SNNs) have seen widespread applications thanks to their higher energy efficiency compared to artificial neural networks (ANNs). However, hardware accelerators dedicated to SNNs without a CPU generally suffer from a lack of flexibility. In this paper, we present a general-purpose RISC-V processor with extended custom instructions designed to efficiently accelerate SNNs. These custom instructions are executed on a tightly-coupled coprocessor, which is a systolic neuron array. This processor with the coprocessor achieves a speedup of $72 \times$ compared to the version without the coprocessor. When implemented on FPGA, the LUT and REG overhead of the coprocessor is about 30% and 22%, respectively.