A 11.4-GHz Dual-Mode Multi-Modulus Divider in 65-nm CMOS

This paper presents a multi-modulus divider (MMD) designed for a $\mathrm{Ka} / \mathrm{Ku}$-band frequency synthesizer used in satellite communications (SATCOM). The MMD is composed of nine cascaded divide-by- 2/3 cells, with the first cell utilizing a novel current mode logic (CML) structure to improve speed with a limited power supply. The remaining cells employ inverter-latch for simplicity. To achieve a large division ratio range from 128 to 255 and 512 to 1023, a switch signal is inserted to change the number of cascaded divide-by- 2/3 cells. With a delta-sigma modulator (DSM), it can operate in either 7-bit fractional mode or 9-bit integer mode. Embedded in a frequency synthesizer, the proposed dual-mode MMD can support maximum operation frequency up to 11.4 GHz. Fabricated in $65-\mathrm{nm}$ CMOS technology, the proposed MMD occupies an area of $0.018 \mathrm{~mm}^{2}$ and consumes 8.6 mW DC power from a 1 V supply.