Area-efficient Architecture of PRINCE Cipher for Resource-constrained Applications

The broad adoption of ubiquitous computing devices has increased security vulnerabilities in the Internet of Things (IoT) field. IoT nodes and RFID devices are secured using the lightweight cryptographic block cipher. The paper offers an area-optimized serial design for the lightweight PRINCE block cipher that makes use of the Shift Register Look-up table (SLR16) register. The proposed architecture has been accomplished or implemented using Hardware Description Language (HDL) in Verilog. The proposed design uses a 16-bit datapath to generate ciphertext in forty clock cycles. Area, throughput, efficiency, and power are among the performance metrics examined in the Virtex series, Spartan-3, and Spartan-6 Field Programmable Gate Arrays (FPGAs). On Spartan-6, the suggested design used 46 slices, had a throughput of 282.94 Mbps, and an efficiency of 6.15 Mbps per slice, and can be beneficial for low-constraint applications.