Design of Clock Tree Distributor with Systematic Scheduler for Stability

Clock Tree distributor (CTD) is a crucial step in the physical design of digital circuits, primarily focused on distributing the clock signal evenly across the chip. While the primary goal of CTD is to minimize skew and ensure timing accuracy, it also indirectly contributes to identifying and mitigating logic faults. The proposed approach discussed the important role of frequency synthesisers in logical fault detection during integration of low power devices. The system considers the stability level analysis of synthesizer results in terms of clock glitches, jitters, skews present in the clocks before utilizing the clocks for integrated devices. The clocks are tested with various levels of sweep stability analysis and latency of sweeping from one frequency to the next shift. The proposed system achieved ±20 ns of sweep shift latency. The sweep stability is tested with 10MHz to 10GHz frequency range with the step size of 100KHz.