A PVT-Insensitive Ultra-Low Voltage Wakeup Timer With a Capacitance Multiplier Based Hybrid Reconfigurable FLL

Modern IoT nodes require wake-up timers with ultra-low power consumption. Different from previous works, this work proposes an ultra-low power wake-up timer that can operate at a supply voltage as low as 0.3 V with PVT-insensitive operation. The circuit is based on a hybrid digital-analog reconfigurable FLL with a capacitance multiplier to reduce power consumption and area overhead. Designed in 65 nm CMOS process, the circuit demonstrates a power consumption of 938 nW at 0.3 V supply. A temperature coefficient of $67.5 \text{ppm} /{ }^{\circ} \text{C}$, and a line sensitivity of $1.19 \% / \text{V}$ are simulated in the temperature/supply range of $0-100^{\circ} \text{C}$ and $0.3-0.6 \ \text{V}$, respectively.