A 22nm Variation-Tolerant Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion with Path Replica

This study proposes a PVTA variation-tolerant adaptive clock duty-cycle controller (DCC) designed to address aging-induced clock duty-cycle distortion (DCD) with clock tree replica and data path replica. The dual-role DCC integrates monitoring and adjustment within a unified framework, offering robust duty-cycle control under variations without specialized calibration. By indirectly monitoring clock and data path replica, this approach overcomes the challenges associated with in-situ monitoring of clock-leaf nodes and provides a reliable foundation to enable DCC. The architecture supports PVTA-calibration-free operation, enabling precise duty-cycle corrections across a frequency range from 250 MHz to 1 GHz. Implemented in a 22 nm PULP CPU, the DCC demonstrates significant improvements in duty-cycle accuracy with an error margin of only 1.1%, while maintaining a rapid response time of 51 cycles at $1 \mathbf{G H z}$.