CongestionNet: VLSI Congestion Prediction Model Using sFCN with MixConv Layers

As IC manufacturing technology advances, the scale and complexity of design rules imposed by manufacturers have increased significantly. The modern Very Large-Scale Integration (VLSI) has a complicated Placement and Routing (P&R) process, which demands multiple iterations to complete the task. This paper introduces a novel model framework, CongestionNet, based on symmetric Fully Convolutional Network (sFCN) to predict congestion hotspots in routing. This model employs MixConv layers and skipped connections to enhance prediction accuracy. Experimental results show that CongestionNet’s Structural Similarity Index Measure (SSIM) reaches $\mathbf{0. 7 3 7 5}$ on ISPD2015 (19% better than existing models), and 0.7935 on CircuitNet-N28 (% better than existing models) respectively. Moreover, with GPU-accelerated prediction method, this model achieves a speed-up ratio of $1,231,557 x$ compared to Cadence Innovus, and a ratio of $1.8 x$ compared to existing deep learning models respectively. To our knowledge, this model is the most accurate FCN-based congestion prediction model in the world and it can greatly assist VLSI back-end designs by significantly shortening convergence time.