Pooling-Priority Architecture for Efficient Deep Learning Acceleration on FPGAs

This study proposed an innovative hardware architecture to accelerate the implementation of convolutional neural networks (CNNs) on mid-to-Iow-end field-programmable gate arrays (FPGA). The design reorders the computation sequence by performing pooling operations before applying ReLU and other activation functions, which effectively reduces the nonlinear processing data volume and thus reduces the computational load and hardware resource requirements, significantly improving the processing efficiency of deep learning tasks. Simulation results verify the correctness of the proposed system, and the hardware power consumption is significantly reduced, with a total power consumption of 0.5293 mW, of which 52% is attributed to switching power. Overall, the proposed hardware architecture provides an efficient solution for implementing CNNs in resource-constrained environments and provides a viable new approach for deploying deep learning models on low-power FPGA platforms, enabling wider application in edge computing and IoT devices.