Invited Paper: A Multi-Phase Multi-Ratio Resonant Switched-Capacitor DC-DC Converter with Improved Power Density

This paper presents a resonant switched-capacitor (ReSC) DC-DC converter for on-chip supply-scaling applications. The proposed DC-DC topology utilizes an arithmetic progression (AP) SC structure and features efficient conversions over wide output-voltage and load-current ranges through multi-mode and multi-phase operations. Specifically, our converter operates in 2phase mode and 5-phase mode under heavy-load and light-load conditions, respectively, to reduce inductor current ripple and switching loss. Implemented in a $65-\mathrm{nm}$ CMOS process with an estimated silicon area of $3 \mathrm{~mm}^{2}$, the proposed converter can regulate an output of 0.5 V to 1.2 V from an input of 1.5 V. The simulated steady-state peak efficiency is 92.84% and the achievable maximum on-chip power density is $0.67 \mathrm{~W} / \mathrm{mm}^{2}$ with a load current of up to 3 A.

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Publication Details

Published
2024-10-25
DOI
https://doi.org/10.1109/icta64028.2024.10860699
Primary Topic
Advanced DC-DC Converters
Type
article
Field-Weighted Citation Impact
0.00

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article

Invited Paper: A Multi-Phase Multi-Ratio Resonant Switched-Capacitor DC-DC Converter with Improved Power Density

Yang Jiang, Nancy Xiuzhi Liu, Pui‐In Mak, Qiaobo Ma et al.
Advanced DC-DC Converters
article

Invited Paper: A Multi-Phase Multi-Ratio Resonant Switched-Capacitor DC-DC Converter with Improved Power Density

Yang Jiang, Nancy Xiuzhi Liu, Pui‐In Mak, Qiaobo Ma, Rui P. Martins
article en

Abstract

This paper presents a resonant switched-capacitor (ReSC) DC-DC converter for on-chip supply-scaling applications. The proposed DC-DC topology utilizes an arithmetic progression (AP) SC structure and features efficient conversions over wide output-voltage and load-current ranges through multi-mode and multi-phase operations. Specifically, our converter operates in 2phase mode and 5-phase mode under heavy-load and light-load conditions, respectively, to reduce inductor current ripple and switching loss. Implemented in a $65-\mathrm{nm}$ CMOS process with an estimated silicon area of $3 \mathrm{~mm}^{2}$, the proposed converter can regulate an output of 0.5 V to 1.2 V from an input of 1.5 V. The simulated steady-state peak efficiency is 92.84% and the achievable maximum on-chip power density is $0.67 \mathrm{~W} / \mathrm{mm}^{2}$ with a load current of up to 3 A.

University of Macau (MO)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 75%
Advanced DC-DC Converters
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