Modeling the Resistance Variation of Heterogeneous Integrated Interconnect Structures under Electrical Stress
This paper studies the resistance change caused by temperature rise due to different currents passing through the sample under electrical stress. The device under test (DUT) is an interconnect structure composed of SAC305 (Sn 96.5%, Ag 3.0%, $\mathrm{Cu} 0.5 \%$) and copper, and the experimental temperature set at $100^{\circ} \mathrm{C}$. The experiment applied $1 \mathrm{~A} \mathrm{DC}, 2 \mathrm{~A} \mathrm{DC}$ and 2.2 A DC currents to the DUT for a total duration of 510 hours. According to the resistance surge phenomenon in the test results, a thermoelectric coupling model is proposed to solve the current temperature-resistance relationship of the interconnect structure, and compared with the test results, the error does not exceed 2%, which verifies its correctness.
Authors
- Huanpeng Wang (ORCID: https://orcid.org/0009-0009-4755-4813)
- Mu‐Sheng Liang (ORCID: https://orcid.org/0000-0001-8382-5961)
- Kun He (ORCID: https://orcid.org/0000-0001-8943-8671)
- Yuehang Xu (ORCID: https://orcid.org/0000-0003-1706-2681)
Institutions
- University of Electronic Science and Technology of China (CN)
Publication Details
- Published
- 2024-10-25
- DOI
- https://doi.org/10.1109/icta64028.2024.10860525
- Citations
- 1
- Primary Topic
- Electronic Packaging and Soldering Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.21