Comparative Analysis of 6T, 8T and 10T SRAM Using 180nm CMOS Technology for IoT Applications
As long as the power is furnished, the Static Random-Access Memory (SRAM) retains the information. SRAM does not demand continuous refreshment, which results better performance and low power usage. For wide variety of IoT applications, low power memory devices are desirable. This paper proposed 6T, 8T and 10T SRAM cells in 180nm CMOS technology, along with layout, parasitic extraction, pre and post layout also. The design of SRAM memory circuits is implemented using Cadence Virtuoso tool and Spectre simulator is used to generate waveform. This advanced SRAM model is the stand-in for IoT (Internet of Things) applications and described about the calculation of delay, noise and power. The proposed SRAM is useful for the devices like PC’s, smart phones, portable memories, embedded devices etc which require less power and high-speed operation.
Authors
- Shweta Madiwalar
- P Shalini
- S. Vijayalakshmi (ORCID: https://orcid.org/0000-0003-1611-2106)
- C. Poongothai
- Vijayashri V. Belgaonkar
- Shanthana Sundaraguru
Institutions
- KLE Technological University (IN)
- KLE Academy of Higher Education and Research (IN)
- Embedded Systems (United States) (US)
- University of Newcastle Australia (AU)
- Newcastle University (GB)
Publication Details
- Published
- 2024-10-25
- DOI
- https://doi.org/10.1109/gccit63234.2024.10862027
- Citations
- 1
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.21
Funders
- Visvesvaraya Technological University